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SSM09N90CGW
N-channel Enhancement-mode Power MOSFET
PRODUCT SUMMARY
BVDSS R DS(ON) ID
DESCRIPTION
The SSM09N90CGW acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for high voltage applications such as AC/DC converters and offline power supplies. The SSM09N90CGW is in a TO-247 (TO-3P) package, which is widely used for commercial and industrial applications, where the greater pin spacing is needed to meet safety specifications. The through-hole package is suitable for vertical mounting, where a small footprint is required on the board, and/or an external heatsink is to be attached.
900V 1.4 7.6A
Pb-free; RoHS-compliant TO-247
G D S
TO-247 (suffix W)
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VGS ID IDM PD EAS
IAS
Parameter Drain-source voltage Gate-source voltage Continuous drain current, TC = 25C TC = 100C Pulsed drain current
1
Value 900 30 7.6 4.8 25 208 1.6
3
Units V V A A A W W/C mJ
A
Total power dissipation, TC = 25C Linear derating factor Single pulse avalanche energy
Avalanche current
120
6
TSTG TJ
Storage temperature range Operating junction temperature range
-55 to 150 -55 to 150
C C
THERMAL CHARACTERISTICS
Symbol
RJC RJA
Parameter
Maximum thermal resistance, junction-case Maximum thermal resistance, junction-ambient
Value
0.6 40
Units
C/W C/W
Notes:
1. Pulse width must be limited to avoid exceeding the safe operating area. 2. Pulse width <300us, duty cycle <2%. 3. Starting Tj=25C, VDD=50V , L=6.8mH , RG=25 , IAS=6A.
8/28/2006 Rev.3.1
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SSM09N90CGW
ELECTRICAL CHARACTERISTICS
Symbol BVDSS Parameter Drain-source breakdown voltage
Breakdown voltage temperature coefficient
(at Tj = 25C, unless otherwise specified)
Test Conditions VGS=0V, ID=1mA Reference to 25C, ID=1mA VGS=10V, ID=3.6A Min. 900 Typ. 0.74 1.25 Max. Units 1.4 V V/C
BV DSS/Tj
RDS(ON)
Static drain-source on-resistance
VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
Gate threshold voltage Forward transconductance
VDS=VGS, ID=250uA VDS=10V, ID=3.6A
2 -
3.6 50.7 12 16 20 16 65 27 516 19
4 10 100 100 80 -
V S uA uA nA nC nC nC ns ns ns ns pF pF pF
Drain-source leakage current
VDS=900V, VGS=0V
VDS=720V ,VGS=0V, Tj = 125C VGS=30V ID=7.2A VDS=540V VGS=10V VDS=450V ID=7.2A RG=6.8 , VGS=10V RD=62.5 VGS=0V VDS=15V f=1.0MHz
Gate-source leakage current Total gate charge
2
Gate-source charge Gate-drain ("Miller") charge Turn-on delay time Rise time Turn-off delay time Fall time Input capacitance Output capacitance Reverse transfer capacitance
2
3097 5000
Source-Drain Diode
Symbol VSD trr Qrr Parameter Forward voltage
2
Test Conditions IS=7.2A, VGS=0V IS=7.2A, VGS=0V, dI/dt=100A/s
Min. -
Typ. 673 9.6
Max. Units 1.5 V ns C
Reverse-recovery time
Reverse-recovery charge
Notes:
1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150C. 2.Pulse width <300us, duty cycle <2%.
8/28/2006 Rev.3.1
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SSM09N90CGW
10 5
T C =25 o C
8
10V 7.0V 5.0V ID , Drain Current (A)
T C =150 o C
4
ID , Drain Current (A)
10V 7.0V 5.0V 4.5V
6
3
4
4.5V
2
V G =4.0V
1
2
V G =4.0V
0 0 2 4 6 8 10 12 14 16 18
0 0 2 4 6 8 10 12 14 16 18
V DS , Drain-to-Source Voltage (V)
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1.2
3.0
I D =3.6A
2.5
V G =10V
1.1
Normalized BVDSS (V)
Normalized RDS(ON)
2.0
1
1.5
1.0
0.9
0.5
0.8
-50 0 50 100 150
0.0 -50 0 50 100 150
Junction Temperature (
o
C)
T j , Junction Temperature ( o C)
Fig 3. Normalized BVDSS vs. Junction Temperature
100 4
Fig 4. Normalized On-Resistance vs. Junction Temperature
10
3
IS (A)
T j = 150 o C
T j = 25 o C
1
VGS(th) (V)
2 1
1.4 1.6
0.1
0 0.2 0.4 0.6 0.8 1 1.2
-50
0
50
100
150
V SD , Source-to-Drain Voltage (V)
T j , Junction Temperature ( o C)
Fig 5. Forward Characteristic of Reverse Diode
Fig 6. Gate Threshold Voltage vs. Junction Temperature
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SSM09N90CGW
15 10000
f=1.0MHz
I D =7.2A VGS , Gate to Source Voltage (V)
12
9
V DS =180V V DS =360V V DS =540V C (pF)
Ciss
1000
6 100
Coss
3
Crss
0 10
0
20
40
60
80
1
5
9
13
17
21
25
29
Q G , Total Gate Charge (nC)
V DS , Drain-to-Source Voltage (V)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
100
1
10
Normalized Thermal Response (Rthjc)
DUTY=0.5
10ms ID (A)
1
0.2
0.1
100ms 1s DC
0.1
0.05
PDM
t
0.02
0.1
T
Duty factor = t/T Peak Tj = PDM x Rthjc + T C
Single Pulse
T c =25 C Single Pulse
0.01 0.1 1 10 100 1000 10000
o
0.01
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
V DS , Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
VDS 90%
VG QG 10V QGS QGD
10% VGS td(on) tr td(off) tf Charge Q
Fig 11. Switching Time Waveform
Fig 12. Gate Charge Waveform
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SSM09N90CGW
PHYSICAL DIMENSIONS - TO-247
E
A
SYMBOLS
Millimeters
MIN NOM MAX
L1
A A1
4.60 1.20 0.80 2.80 1.80 0.55 1.45 19.70 15.40 5.15 16.20 3.60 3.30
4.80 1.40 1.00 3.00 2.00 0.60 1.50 19.90 15.60 5.45 16.50 3.80 3.50
5.00 1.60 1.20 3.20 2.20 0.75 1.65 20.10 15.80 5.75 16.80 4.00 3.70
c1
D
b b1
b2
c c1
D E
L3
b1
b2 A1 L c
b
e
L L1 L3
1. All dimensions are in millimeters. 2. Dimensions do not include mold protrusions.
e
PART MARKING - TO-247
PACKING:
Moisture sensitivity level MSL3
1000pcs in tubes packed inside a moisture barrier bag (MBB).
09N90CGW YWWSSS
PART NUMBER: 09N90CGW = SSM09N90CGW DATE/LOT CODE: Y = last digit of the year WW = work week (01 -> 52) SSS = lot code sequence
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.
8/28/2006 Rev.3.1
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